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16 Mbit LPC Flash
SST49LF160C
Advance Information
Abort Mechanism
If LFRAME# is driven low for one or more clock cycles after
the start of a bus cycle, the cycle will be terminated. The
host may drive the LAD[3:0] with ‘1111b’ (ABORT nibble) to
return the interface to ready mode. The ABORT only
affects the current bus cycle. For a multi-cycle command
sequence, such as the Erase or Program commands,
ABORT doesn’t interrupt the entire command sequence,
only the current bus cycle of the command sequence. The
host can re-send the bus cycle for the aborted command
and continue the command sequence after the device is
ready again.
Response to Invalid Fields for
LPC Memory Cycle
During an on-going LPC bus cycle, the SST49LF160C will
not explicitly indicate that it has received invalid field
sequences. The response to specific invalid fields or
sequences is described as follows:
ID mismatch: ID information is included in the address
bits of every LPC Memory cycle. Address bits [A 25 :A 23 ,
A 21 ] are used to select the device with proper IDs. The
SST49LF160C will compare the ID bits in the address field
with ID[3:0]. If the ID bits in the address do not correspond
to the hardware ID pins the device will ignore the cycle. See
Device Commands section for details.
Address out of range: The address sequence is 8
fields long (32 bits). The address bits [A 25 :A 23 , A 21 ] for the
SST49LF160C are used to select the device with proper
IDs. Unused most significant address bits must be set to
“1” during LPC protocol transfer. Address A 22 has the spe-
cial function of directing Read and Write operations to the
flash core (A 22 =1) or to the register space (A 22 =0).
For the Boot Device (ID[3:0]=0000b), the SST49LF160C
decodes the physical addresses of the Top 128 KByte
Blocks (including Boot Block) at both system memory
ranges indicated in Table 6.
TABLE 6: B OOT D EVICE
P HYSICAL A DDRESSES D ECODING
Also mapped at
Once valid START, CYCTYPE + DIR, and address range
(including ID bits) are received, the SST49LF160C will
always complete the bus cycle. However, if the device is
busy performing a flash Erase or Program operation, no
new internal memory Write will be executed. As long as the
states of LAD[3:0] and LFRAME# are known, the response
of the SST49LF160C to signals received during the LPC
cycle is predictable.
Memory Range
FFFF FFFFH - FFFE 0000H
Memory Range
000F FFFFH - 000E 0000H
?2006 Silicon Storage Technology, Inc.
14
S71315-00-000
4/06
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相关代理商/技术参数
SST49LF160C-33-4C-NHE_ 制造商:Microchip Technology Inc 功能描述:
SST4H-D 功能描述:电缆束带 Cable Tie, 2-Piece, 14.8"L (376mm), Ligh RoHS:否 制造商:Phoenix Contact 产品:Cable Tie Mounts 类型:Adhesive 颜色:Black 材料:Acrylonitrile Butadiene Styrene (ABS) 长度:19 mm 宽度:19 mm 抗拉强度:
SST4H-D0 功能描述:电缆束带 14.8" BLK CABLE TIE RELEAS WEATHER RES RoHS:否 制造商:Phoenix Contact 产品:Cable Tie Mounts 类型:Adhesive 颜色:Black 材料:Acrylonitrile Butadiene Styrene (ABS) 长度:19 mm 宽度:19 mm 抗拉强度:
SST4H-D30 功能描述:电缆束带 Cable Tie, 2-Piece, 14.8"L (376mm), Ligh RoHS:否 制造商:Phoenix Contact 产品:Cable Tie Mounts 类型:Adhesive 颜色:Black 材料:Acrylonitrile Butadiene Styrene (ABS) 长度:19 mm 宽度:19 mm 抗拉强度:
SST4HH-D 制造商:Panduit Corp 功能描述:
SST4HH-D30 功能描述:电缆束带 Cable Tie, Heavy Head, 2-Piece, 14.8" (3 RoHS:否 制造商:Phoenix Contact 产品:Cable Tie Mounts 类型:Adhesive 颜色:Black 材料:Acrylonitrile Butadiene Styrene (ABS) 长度:19 mm 宽度:19 mm 抗拉强度:
SST4H-L 功能描述:电缆束带 Cable Tie 2-Piece 14.8"L (376mm) Lt RoHS:否 制造商:Phoenix Contact 产品:Cable Tie Mounts 类型:Adhesive 颜色:Black 材料:Acrylonitrile Butadiene Styrene (ABS) 长度:19 mm 宽度:19 mm 抗拉强度:
SST4H-L 制造商:Panduit Corp 功能描述:Cable Ties Cable Bundle Diameter Max.:4.